The invention relates to testing integrated circuits, and, more particularly, to a method and apparatus for programmably delaying the start of an array built-in self-test (ABIST) until the ABIST memory arrays have been started and the power supply voltage on the integrated circuit has stabilized.
Array built-in self-test (ABIST) is used to test the memory arrays that are contained in high-end processors. ABIST allows the memory arrays to be tested at and above system clock speeds using a locally generated pattern set that verifies memory array functionality.
Conceptually, the ABIST approach is based on the realization that much of a circuit tester""s electronics is semi-conductor based, just like the products it is testing, and that many of the challenges and limitations in testing lie in the interface to the Device Under Test (DUT). The ABIST approach can be described as an attempt to move many of the already semiconductor-based test equipment functions into the products under test and eliminate the complex interfacing. One of the major advantages ABIST has over other means of testing memory arrays is that the operation of the test is self-contained. All of the circuitry required to execute the test at-speed is contained within the integrated circuit. Very limited external controls are needed, so ABIST can be run at all levels of packaging (wafer, TCA, module and system) without requiring expensive external test equipment.
ABIST utilizes a boundary-scan design-for-test (DFT) technique. The DFT technique consists of placing a scannable memory element, or boundary-scan chain, adjacent to each integrated circuit I/O so that signals at the integrated circuit boundaries can be controlled and observed using scan operations and without direct contact with the integrated circuit. All internal storage elements are modified such that in test mode they form individual stages of a shift register for scanning in test data stimuli and scanning out test responses. Execution of finite-state-machine ABIST involves initializing the integrated circuit for ABIST, usually through the scannable memory element, and applying a sufficient number of system clocks, either externally or through a self-generated clock, for the finite-state machine to reach its final state.
In contrast, execution of programmable ABIST involves scanning the ABIST program to be applied into a custom microcode array, and each instruction is decoded, executed, and applied to the array by the ABIST microprocessor. During the programmable ABIST test, a controller based on a programmable-state machine is used to algorithmically generate a variety of memory test sequences. These test patterns are applied to the embedded memory array at cycle speed. Programmable ABIST, in contrast to finite-state machine ABIST allows for the application of a testing scheme that is flexible enough to help diagnose potential problems, stress memory array performance, and provide production-level testing ability.
Over time the memory arrays have become larger and faster and, therefore, consume more power than preceding generations of integrated circuits. When clocks are first applied to the memory arrays during the ABIST test sequence, there is a sudden large current draw from the integrated circuit power supply. Because the integrated circuit power supplies cannot respond with additional current for many microseconds, various levels of capacitors are used to supply the transient currents until the power supplies can respond. During this time, the integrated circuit power supply voltage will start to droop as the capacitors lose charge until the power supply can respond with the required current. The power supply voltage will continue to xe2x80x9cringxe2x80x9d until a steady state DC current condition is achieved.
CMOS circuit speed is directly affected by power supply voltage. Circuits will run faster with higher voltage and slower with lower voltage. During the initial cycles of the ABIST test, the power supply will be fluctuating and the minimum cycle time for the ABIST test will vary with the power supply voltage. The performance of the memory arrays cannot be accurately measured during this time.
An exemplary embodiment of the invention is a method and apparatus for delaying the start of an array built-in self-test (ABIST) until after the ABIST memory arrays have been started. The length of the delay is determined by the value in a programmable delay located on the integrated circuit. The initiation of the ABIST test is delayed by the time specified in the programmable delay.